The present invention relates generally to analog-digital converters, in particular to successive approximation register (SAR) converters. In particular, the present invention relates to measures for improving the accuracy of an SAR converter.
SAR converters for analog-digital conversion are well known in the art. In particular, SAR converters are frequently used in integrated CMOS devices since they provide a wide range of achievable resolution and conversion time and have competitive power efficiency. Furthermore, SAR converters can be implemented by optimally utilizing the advantages of the CMOS technology, which are small-sized switches and capacitors having well-defined relative capacitances over a broad range.
According to a well-known topology, SAR converters include at least one capacitor bank on a comparison line. The capacitor bank has capacitors of different values, usually having a relation with a factor of 2n (n=integer) between the capacitances. Each capacitor of the capacitor bank is connected between the comparison line and a reference potential line, a ground potential line and an input signal line. Each capacitor is further associated with a switch, so that the respective capacitor can be connected to one of the reference potential line, the ground potential line and the input signal line. The SAR analog-digital converter further has a decision latch for receiving and evaluating the comparison line potential, e.g., with respect to a given ground potential. Furthermore, a logic block assesses the determination results of a previous determination step and accordingly applies a respective potential to a respective capacitor.
In a sampling phase, a voltage level of an input signal (positive voltage level with respect to a ground potential) applied to the input signal line is stored on each capacitor of the capacitor bank while a ground potential is applied to the comparison line. Before starting a conversion phase, the reference potential is applied to each capacitor to present the sampled input voltage and to redistribute charges stored in each of the capacitors to the comparison line. Then, the capacitors are connected with the ground potential line in successive steps, i.e., from the highest capacitance to the lowest capacitance, while it is determined after each step whether the resulting voltage on the input signal line is above or below a predetermined threshold (ground potential). The determination results are stored as result bits in a register. Depending on the determination result, the recently switched capacitor is reset or kept in the set state.
As mentioned above, the capacitors of the capacitor bank usually have a relation with a factor of 2n (n=integer) between the capacitances, so that the factor between the capacitor having the lowest capacitance and the capacitor having the highest capacitance depends on the resolution of the analog-digital converter. Usually, the factor for such a topology equals 2B−1, wherein B corresponds to the resolution in bits of the analog-digital converter. For a 16-bit analog-digital converter, the factor between the lowest and the highest capacitance is therefore 32,768.